SM5964_06 Datasheet, PDF (13/26 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller 64KB ISP flash & 1KB RAM embedded

SyncMOS Technologies International, Inc.
SM5964
8-Bits Micro-controller
64KB ISP flash & 1KB RAM embedded
4.1 Watch Dog Timer Registers: WDTC and SCONF
Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
bit-7
bit-0
WDTE reserved** Clear Unused Unused
PS2
PS1
PS0
Read / Write:
R/W
-
R/W
-
-
R/W
R/W
R/W
Reset value:
0
*
0
*
*
0
0
0
** Keep to “0” when write WDTC (9FH).
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer reset bit
PS[2:0] : Overflow period select bits
PS [2:0]
000
001
010
011
100
101
110
111
Divider(OSC in)
8
16
32
64
128
256
512
1024
Time Period (ms) @ 40 MHZ
13.12.048
26.21
52.42
104.8
209.71
419.43
838.86
1677.72
Watch Dog Timer Register - System Control Register (SCONF, $BF)
Read / Write:
Reset value:
bit-7
WDR
R/W
0
Unused
-
*
Unused
-
*
Unused
-
*
Unused
-
*
ISPE
R/W
0
OME
R/W
1
bit-0
ALEI
R/W
0
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever un-predicted reset happened.
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.2 SM5964 08/2006
13