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VP5225 Datasheet, PDF (2/3 Pages) Supertex, Inc – P-Channel Enhancement-Mode Vertical DMOS FET
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VP5225
Thermal Characteristics
Package
ID
(continuous)†
(mA)
ID
(pulsed)
(A)
Power Dissipation
@TA = 25OC
(W)
θjc
(OC/W)
θja
(OC/W)
IDR†
(mA)
IDRM
(A)
3-LeadTO-252 (D-PAK)
645
3.0
2.5‡
6.25
50‡
645
3.0
Notes:
† ID (continuous) is limited by max rated Tj of 150OC.
‡ Mounted on FR4 board, 25mm x 25mm x 1.57mm
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
-250 -
-
V VGS = 0V, ID = -250µA
VGS(th) Gate threshold voltage
-1.0
-
-2.4
V VGS = VDS, ID= -1.0mA
ΔVGS(th) Change in VGS(th) with temperature
-
-
4.5 mV/OC VGS = VDS, ID= -1.0mA
e IGSS Gate body leakage
-
-
-100
nA VGS = ± 20V, VDS = 0V
t IDSS Zero gate voltage drain current
-
-
-10
µA VGS = 0V, VDS = Max Rating
-
-
-1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current
-2.5
-
-
A VGS = -10V, VDS = -25V
RDS(ON) Static drain-to-source on-state resistance
-
-
-
5.0
Ω
VGS = -4.5V, ID = -250mA
-
3.0
VGS = -10V, ID = -1.0A
e ΔRDS(ON) Change in RDS(ON) with temperature
-
-
1.7 %/OC VGS = -10V, ID = -1.0A
GFS Forward transductance
500
-
- mmho VDS = -25V, ID = -200mA
l CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
-
-
400
VGS = 0V,
-
-
150
pF VDS = -25V,
-
-
50
f = 1.0MHz
td(ON)
o tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
-
-
20
-
-
30
VDD = -25V,
-
-
60
ns ID = -500mA,
RGEN = 25Ω
-
-
30
VSD Diode forward voltage drop
-
-
-1.8
V VGS = 0V, ISD = -500mA
s trr
Reverse recovery time
-
300
-
ns VGS = 0V, ISD = -500mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulsed test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
b Switching Waveforms and Test Circuit
0V
INPUT
O-10V
10%
90%
PULSE
GENERATOR
RGEN
t(ON)
t(OFF)
td(ON)
tr
td(OFF)
tF
D.U.T.
0V
INPUT
Output
OUTPUT
VDD
10%
90%
90%
10%
RL
VDD
2
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