HV430_14 Datasheet, PDF (1/9 Pages) Supertex, Inc – High-Voltage Ring Generator

Supertex inc.
HV430
High-Voltage Ring Generator
Features
► 105Vrms ring signal
► Output overcurrent protection
► 5.0V CMOS logic control
► Logic enable/disable to save power
► Adjustable deadband in single-control mode
► Power-on reset
► Fault output for problem detection
Applications
► Line access cards
► Set-top/Street box
The RESET input functions as a power-on reset when
connected to an external capacitor. The FAULT output
indicates an overcurrent condition and is cleared after 4
consecutive cycles with no overcurrent condition. A logic low
on RESET or ENABLE clears the FAULT output. It is active-
low and open-drain to allow wire OR’ing of multiple drivers.
P_GATE and N_GATE are controlled independently by logic inputs
P_IN and N_IN when the MODE pin is at logic high. A logic high on
P_IN will turn on the external P-channel MOSFET. Similarly, a
logic high on N_IN will turn on the external N-channel MOSFET.
Lockout circuitry prevents the N and P switches from turning
on simultaneously. A pulse width limiter restricts pulse widths
to no less than 100 - 200ns.
General Description
The Supertex HV430 is a high voltage PWM ring generator
integrated circuit. The high voltage outputs, V_PGATE and
V_NGATE, are used to drive the gates of external high voltage
N-channel and P-channel MOSFETs in a push-pull
configuration. Overcurrent protection is implemented for
both the P-channel and N-channel MOSFETs. External
sense resistors set the over-current trip point.
For applications where a single control input is desired, the
MODE pin should be connected to SGND. The PWM control
signal is then input to the N_IN pin. A user-adjustable deadband
in the control logic ensures break-before-make on the outputs,
thus avoiding cross conduction on the high voltage output
during switching. A logic high on N_IN will turn the external P-
Channel MOSFET on and the N-Channel off, and vice versa.
The IC can be powered down by applying a logic low on the
ENABLE pin, placing both external MOSFETs in the off state.
Functional Block Diagram
V_DD
FAULT
De-glitcher
clk reset
PIN
MODE
DEADBAND
NIN
Control
Logic
+5.0V
V_DD
VPP2
V_PP2
Regulator
VPP1
Down
Translator
Up
Translator
Current
Trip
P
Driver
Up
Translator
N
Driver
VPSEN
VPGATE
VNGATE
V_PP1
R_SENSE
Ringer
Output
ENABLE
RESET
V_DD
10µA
Doc.# DSFP-HV430
A031414
Down
Translator
Current
Trip
SIG PWR
GND GND
V_NN2
Regulator
VNN2
VNSEN
VNN1
R_SENSE
V_NN1
Supertex inc.
www.supertex.com