SMH4812_09 Datasheet, PDF(9/18 Page) Summit Microelectronics, Inc.

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SMH4812_09 Datasheet, PDF (9/18 Pages) Summit Microelectronics, Inc. – Distributed Power Hot-Swap Controller

◁

SMH4812

Preliminary

Under-Voltage Hysteresis

The Under-Voltage comparator input may be configured

with a programmable level of hysteresis. The compare

level may be set in steps (up to 15) of 62.5mV below 2.5V.

The default under-voltage hysteresis level is set to

62.5mV.

Soft Start Slew Rate Control

Once all of the preconditions for powering up the DC/DC

controllers have been met, the SMH4812 provides a

means to soft start the external power FET. It is important

to limit in-rush current to prevent damage to the add-in

card or disruptions to the host power supply. For example,

charging the filter capacitance (normally required at the

input of the DC/DC controllers) too quickly may generate

very high current. The VGATE output of the SMH4812 is

current limited to IVGATE, allowing the slew rate to be easily

modified using external passive components. The slew

rate may be found by dividing IVGATE by the gate-to-drain

capacitance placed on the external FET. A complete

design example is given in the Applications Section.

Load Control â Sequencing the Secondary Sup-

plies

Once power has been ramped to the DC/DC controllers,

two conditions must be met before the PG# output can be

enabled: the Drain Sense voltage must be below 2.5V,

and the VGATE voltage must be greater than VDD â VGT.

The Drain Sense input helps ensure that the power MOS-

FET is not absorbing too much steady state power from

operating at a high V . This sensor remains active at all

times (except during the current regulation period). The

VGATE sensor makes sure that the power MOSFET is

operating well into its saturation region before allowing the

loads to be switched on. Once VGATE reaches VDD â VGT

this sensor is latched.

When the external MOSFET is properly switched on the

PG# output may be enabled (if ENPG is high). Output PG#

is activated after a tPGD delay. The delay time is program-

mable from 50Âµs to 160ms.

timer allows the SMH4812 to ignore the state of the FS#

input until the timer period expires. The FS# input must be

driven high by the end of this timer period. A low level on

this input will cause a Fault condition, driving FAULT# low

and shutting off the VGATE and PG# outputs.

The purpose of the holdoff timer is to allow enough time for

devices on the secondary side of the DC/DC controllers to

power up and stabilize. This unique feature of the

SMH4812 allows supervisory circuits such as an SMS44

to control the shutdown of the primary side soft start circuit,

even though the secondary side initially has no power.

The FS# input can be programmed to act as a second

ENPG input controlling the PG# output.

Circuit Breaker Operation

The SMH4812 provides a number of circuit breaker func-

tions to protect against over current conditions. A sus-

tained over-current event could damage the host supply

and/or the load circuitry. The boardâs load current passes

through a series resistor (RS) connected between the

MOSFET source (which is tied to CBSENSE) and VSS.

The breaker trips whenever the voltage drop across R is

greater than 50mV for more than tCBD (a programmable

filter delay ranging from 10Âµs to 500Âµs).

Quick-TripTM Circuit Breaker

Additionally, the SMH4812 provides a Quick-Trip feature

that will cause the circuit breaker to trip immediately if the

voltage drop across RS exceeds VQCB. The Quick-Trip

level may be set to 60mV, 100mV (default), 200mV, or the

feature may be disabled.

CBSENSE

<TCBD

VQCB

50mV

The PG# output has a 12V withstand capability, so high

voltages must not be connected to this pin. A bipolar

transistor or an opto-isolator can be used to boost the

withstand voltage to that of the host supply. See Figure 9

for connections.

VGATE

TFSTSHTDN

Forced Shutdown â Secondary Feedback

The Forced Shutdown signal (FS#) is an active low input

that provides a method of receiving feedback from the

secondary side of the DC/DC controllers. A built-in holdoff

2055 Fig04

Figure 4. Circuit Breaker Quick Trip Response

SUMMIT MICROELECTRONICS, Inc.

2055 4.1 03/27/09

▷