S9418 Datasheet, PDF (2/10 Pages) Summit Microelectronics, Inc. – Quad 8-Bit Nonvolatile DACPOT™ Electronic Potentiometer With a Mute Control Input

S9418
PINOUT and SIGNAL DEFINITION
VREFH1 1
VREFH0 2
VDD 3
RDY/BSY 4
CLK 5
CS 6
DI 7
DO 8
MUTE ₉
GND 10
20 VREFH2
19 VREFH3
18 VOUT0
17 VOUT1
16 VOUT2
15 VOUT3
14 VREFL3
13 VREFL2
12 VREFL1
11 VREFL0
2023 ILL1 1.2
Pin Name Function
1, 2 VREFH
20, 19
Vreference High:
VREFH ≤ VDD > VREFL
3
VDD
Power Supply Voltage
4 RDY/BSY Ready/Busy: open drain output
indicating status of nonvolatile
write operations
5 CLK
Clock Input Pin: used for serial
data communication
6 CS
Chip Select: When high deselects
the device and places it in a low
power mode
7 DI
Data Input: serial data input pin
8 DO
Data Output: serial data output pin
9 MUTE
When active forces VOUT to VREFL
10 GND
Power Supply Ground
11, 12 VREFL
13, 14
Vreference Low
15, 16 VOUT
17, 18
DAC Output: buffered D to A
converter output
The analog outputs of the S9418 can be programmed to
any one of 256 individual voltage steps. Each step value
is 1/256^th of the voltage differential between VrefH and
VrefL of the respective DAC. Once programmed these
settings can be retained in nonvolatile memory during all
power conditions and will be automatically recalled upon
a power-up sequence. Each DAC can be independently
read without affecting the output voltage during the read
cycle. In addition each output can be adjusted an unlim-
ited number of times without altering the value stored in
the nonvolatile memory.
DEVICE OPERATION
Analog Section
The S9418 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts 8-bit digital inputs into equivalent analog
output voltages in proportion to the applied reference
voltage.
Reference inputs
The voltage differential between the V_REFL and V_REFH
inputs sets the full-scale output voltage for its respective
DAC. V_REFL must be equal to or greater than ground
(positive voltage). V_REFH must be greater (more positive)
than V_REFL or equal to V_DD.
Output Buffer Amplifiers
The voltage outputs are from precision unity-gain follow-
ers that can slew up to 1V/µs. The outputs can swing from
V_REFL to V_REFH. With a 0V to 5V output transition the
amplifier outputs typically settle to 1LSB in 50µs.
DIGITAL INTERFACE
The S9418 employs a common 4-wire serial interface. It
is comprised of a Clock (CLK), Chip Select (CS) and Data
In (DI) input and a Data Out (DO) output. Data is clocked
into the device on the clock’s rising edge and out of the
device on the clock’s falling edge. Data is shifted in and
out MSB first. DO only becomes active after the device
has been selected and after a valid read command and
address has been received.
All data transfers are initiated after CS goes LOW and a
logic ‘1’ is clocked into the device. This first data transfer
is the start bit and must precede all operations. Following
the start bit are two command bits used to specify which
of four commands to execute. The next two bits are the
address bits used to select one of the four DACs. The
action of the next eight clock cycles will be dependent
upon the command issued.
2023 1.5 4/24/99
2