S9408S Datasheet, PDF (2/10 Pages) Summit Microelectronics, Inc. – Serial Input, Quad 8-Bit Nonvolatile DACPOT

S9408
PINOUT and SIGNAL DEFINITION
20-Pin PDIP
or 20-Pin SOIC
VREFH1 1
20 VREFH2
VREFH0 2
19 VREFH3
VDD 3
18 VOUT0
RDY/BSY# 4
17 VOUT1
CLK 5
16 VOUT2
CS# 6
15 VOUT3
DI 7
14 VREFL3
DO 8
13 VREFL2
00/REG# 9
12 VREFL1
GND 10 11 VREFL0
2015 T PCon 2.0
Pin Name
Function
1, 2 V_REFH
20, 19
3
V_DD
Vreference High:
VREFL < VREFH - VDD
Power Supply Voltage
4 RDY/BSY# Ready/Busy: open drain output
indicating status of nonvolatile
write operations
5 CLK
Clock Input Pin: used for serial
data communication
6 CS#
Chip Select: When high deselects
the device and places it in a low
power mode
7 DI
Data Input: serial data input pin
8 DO
Data Output: serial data output pin
9 00/REG# Power On Recall Option Input
10 GND
Power Supply Ground
11, 12 V_REFL
13, 14
Vreference Low:
VREFH > VREFL • GND
15, 16 VOUT
17, 18
DAC Output: buffered D to A
converter output
The analog outputs of the S9408 can be programmed to
any one of 256 individual voltage steps. Each step value
is 1/256^th of the voltage differential between V_REFH and
V_REFL of the respective DAC. Once programmed these
settings can be retained in nonvolatile memory during all
power conditions and will be automatically recalled upon
a power-up sequence. Each DAC can be independently
read without affecting the output voltage during the read
cycle. In addition, each output can be adjusted an unlim-
ited number of times without altering the value stored in
the nonvolatile memory.
DEVICE OPERATION
Analog Section
The S9804 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts 8-bit digital inputs into equivalent analog
output voltages in proportion to the applied reference
voltage.
Reference inputs
The voltage differential between the V_REFL and V_REFH
inputs sets the full-scale output voltage for its respective
DAC. V_REFL must be equal to or greater than ground
(positive voltage). V_REFH must be greater (more positive)
than V_REFL and less than or equal to V_DD.
Output Buffer Amplifiers
The voltage outputs are precision unity-gain followers that
slew up to 1V/µs. The outputs can swing from V_REFL to
V_REFH. With a 0V to 5V output transition the amplifier
outputs typically settle to 1LSB in 40µs.
DIGITAL INTERFACE
The S9408 employs a common 4-wire serial interface. It
is comprised of a Clock (CLK), Chip Select (CS#), Data In
(DI) and Data Out (DO). Data is clocked into the device on
the clock’s rising edge and out of the device on the clock’s
falling edge. Data is shifted in and out MSB first. DO only
becomes active after the device has been selected and
after a valid read command and address has been re-
ceived.
All data transfers are initiated after CS# goes low and a
logic ‘1’ is clocked into the device. This first data transfer
is the start bit and must precede all operations. Following
the start bit are two command bits used to specify which
of four commands to execute. The next two bits are the
address bits used to select one of the four DACs. The
action of the next eight clock cycles will be dependent
upon the command issued.
2015 2.2 8/2/00
2
SUMMIT MICROELECTRONICS, Inc.