SMH4802_09 Datasheet, PDF (17/19 Pages) Summit Microelectronics, Inc. – Programmable -48V Hot-Swap Controller with Forced Shut Down

SMH4802
Preliminary Information
PROGRAMMING INFORMATION (Continued)
Register Access
Master/Slave Protocol
The SMH4802 contains a 2-wire bus interface for register
access as explained in the previous section. This bus is
highly configurable while maintaining the industry stan-
dard protocol. The SMH4802 responds to one of two
selectable Device Type Addresses: 1010BIN, generally
assigned to NV-memories, or 1011BIN, which is the default
address for the SMH4802. The Device Type Address is
assigned by programming bit 3 of Register 8.
Register accesses are also programmable using bits 2
and 1 of Register 8. Accesses can be denied (no reads
or writes), read only, or read/write (default state).
The master/slave protocol defines any device that sends
data onto the bus as a transmitter and any device that
receives data as a receiver. The device controlling data
transmission is called the Master and the controlled
device is called the Slave. The SMH4802 is always a
Slave device since it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time, because a change on the data line while SCL is high
is interpreted as either a Start or a Stop condition.
Register Bit Maps
The SMH4802 has three address pins (A2, A1 and A0)
associated with the 2-wire bus. The SMH4802 can be
configured to respond only to the proper serial data string
of the Device Type Address and specific bus addresses
(Register 8, bit 0 set); or to the Device Type Address and
any bus address (Register 8, bit 0 cleared).
The SMH4802 has eight user programmable, nonvolatile
configuration registers. Although 8-bit data transfers are
used for reading and writing the registers, only the 4 least
significant bits of each register are utilized by the device.
Therefore, in each of the following registers, bits 7 through
4 are left blank. Bits 3 through 0 are used as shown for
each register.
DEFAULT CONFIGURATION REGISTER SETTINGS - SMH4802-169
Register
Hex
Contents
Description
R02
9 Over-current delay and Quick-Trip over-current reference level.
R03
2 Power good sequencing delay. CB mode enable.
R04
B PG# enable, over-/under-voltage filter delay, circuit breaker cycle time.
R05
C Non-volatile fault latch enable, FS# function control.
R06
C Under- and over-voltage filter enables, VGATE current regulation control.
R07
9 Under-voltage hysteresis control.
R08
1
I²C control, including device type address, configuration register
read/write status, and slave address response control.
R09
9 Power good sequence speed.
R0C
0 Non-volatile fault latch. Set by hardware when fault is detected.
2062 Reg Table
SUMMIT MICROELECTRONICS, Inc.
2062 2.4 03/27/09
17