SMH4802_09 Datasheet, PDF (16/19 Pages) Summit Microelectronics, Inc. – Programmable -48V Hot-Swap Controller with Forced Shut Down

SMH4802
Preliminary Information
PROGRAMMING INFORMATION (Continued)
After the word address Acknowledge is received by the
Master it immediately reissues a Start condition followed
by another Slave address field with the R/W bit set to
Read. The SMH4802 responds with an Acknowledge and
then transmits the 8 data bits stored at the addressed
location. At this point, the Master sets the SDA line to
NACK and generates a Stop condition. The SMH4802
discontinues data transmission and reverts to its standby
power mode.
Sequential Reads
Sequential reads can be initiated as either a current
address read or a random access read. The first word is
transmitted as with the other byte Read modes (current
address byte Read or random address byte Read).
However, the Master now responds with an Acknowl-
edge, indicating that it requires additional data from the
SMH4802.
The SMH4802 continues to output data for each Acknowl-
edge received. The Master sets the SDA line to NACK and
generates a Stop condition. During a sequential Read
operation the internal address counter is automatically
incremented with each Acknowledge signal.
For Read operations all address bits are incremented,
allowing the entire array to be read using a single Read
command. After a count of the last memory address the
address counter rolls over and the memory continues to
output data.
S
T
A
R
R
/
Master _T
W
NS
A
AT
C
CO
K
KP
SDA
1 01 0 xxxRxxx xxxxx ^{xx xx}
Slave
A
C
K
2062 Fig14
Figure 14. Read Protocol
S
T
S
A
R
T
R
/
O
Master _T
W
P
SDA
1 0 1 0 x x xW x x x x x x x x x x x x
Slave
A
A
A
C
C
C
K
K
K
2062 Fig15
Figure 15. Write Protocol
Master
SDA
Slave
S
T _DEVICE
A
R
IDENTIFIER
Typical Write Operation
S
T
O
T
P
1
0
1
0
AA
21
A
0
R
/
W
AA A A A A A A
76 5 4 3 2 1 0
DDDDDDDD
76543210
A
A
A
BUS
ADDRESS
C
K
C
K
C
K
S
T _DEVICE
Master
A
R
IDENTIFIER
T
Typical Read Operation
S
T
A
R
T
SDA
10
1
0
AA
21
A
0
R
/
W
AA A A A A A A
76 5 4 3 2 1 0
1
0
1
0
AA
21
A
0
R
/
W
NS
AT
CO
KP
DDDDDDDD
76543210
Slave
A
BUS
C
ADDRESS ^K
A
C
K
A
C
2062 Fig16
K
Figure 16. Sequential Bus Cycles
16
2062 2.4 03/27/09
SUMMIT MICROELECTRONICS, Inc.