SMH4042 Datasheet, PDF (12/28 Pages) Summit Microelectronics, Inc. – Hot Swap™ Controller

SMH4042
MEMORY OPERATION
The SMH4042 memory is configured as a 512 x 8 array.
Data are read and written via an industry standard two-
wire interface. The bus was designed for two-way, two-
line serial communication between different integrated
circuits. The two lines are a serial data line (SDA), and a
serial clock line (SCL). The SDA line must be connected
to a positive supply by a pull-up resistor, located some-
where on the bus
Input Data Protocol
The protocol defines any device that sends data onto the
bus as a “transmitter” and any device that receives data as
a “receiver.” The device controlling data transmission is
called the “master” and the controlled device is called the
“slave.” In all cases, the SMH4042 will be a “slave” device,
since it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock
HIGH time, because changes on the data line while SCL
is HIGH will be interpreted as start or stop condition.
START and STOP Conditions
When both the data and clock lines are HIGH, the bus is
said to be not busy. A HIGH-to-LOW transition on the data
line, while the clock is HIGH, is defined as the “START”
condition. A LOW-to-HIGH transition on the data line,
while the clock is HIGH, is defined as the “STOP”
condition.
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
the master or the slave, will release the bus after transmit-
ting eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to ACKnowledge that it received
the eight bits of data.
The SMH4042 will respond with an ACKnowledge after
recognition of a START condition and its slave address
byte. If both the device and a write operation are selected,
the SMH4042 will respond with an ACKnowledge after the
receipt of each subsequent 8-bit word. In the READ mode,
the SMH4042 transmits eight bits of data, then releases
the SDA line, and monitors the line for an ACKnowledge
signal. If an ACKnowledge is detected, and no STOP
condition is generated by the master, the SMH4042 will
continue to transmit data. If an ACKnowledge is not
detected, the SMH4042 will terminate further data trans-
missions and awaits a STOP condition before returning to
the standby power mode.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see below). For the SMH4042 this is fixed as 1010[B].
The next two bits select one of four possible devices on
the bus. The state of the hardwired inputs (A2 and A1)
correspond to the serial bit stream A2 and A1 in the slave
address. The next bit is the block select bit, effectively the
MSB of the byte address.
Read/Write Bit
The last bit of the data stream defines the operation to be
performed. When set to “1,” a read operation is selected;
when set to “0,” a write operation is selected.
DEVICE
IDENTIFIER
BUS
ADDRESS
1 0 1 0 A2 A1 B0 R/W
Slave Address Byte
2037 ILL15.0
WRITE OPERATIONS
The SMH4042 allows two types of write operations: byte
write and page write. A byte write operation writes a single
byte during the nonvolatile write period (tWR). The page
write operation allows up to 16 bytes in the same page to
be written during tWR.
Byte Write
After the slave address is sent (to identify the slave
device, and a read or write operation), a second byte is
transmitted which contains the 8 bit address of any one of
the 512 words in the array. Upon receipt of the word
address, the SMH4042 responds with an ACKnowledge.
After receiving the next byte of data, it again responds with
an ACKnowledge. The master then terminates the trans-
fer by generating a STOP condition, at which time the
SMH4042 begins the internal write cycle. While the inter-
nal write cycle is in progress, the SMH4042 inputs are
disabled, and the device will not respond to any requests
from the master.
Page Write
The SMH4042 is capable of a 16-byte page write opera-
tion. It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word, the master can transmit up to 15 more
bytes of data. After the receipt of each byte, the SMH4042
will respond with an ACKnowledge.
2037 8.0 8/8/00
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