SMH4042 Datasheet, PDF (10/28 Pages) Summit Microelectronics, Inc. – Hot Swap™ Controller

SMH4042
issue with a dual supply application. But in a single supply
application these two pins must be shorted and VSEL
conditioned as explained above.
Programmable Vtrip Thresholds
The host voltage monitors and the backend voltage
monitors are programmable (by the factory) and provide
a number of options to the end user. The VCC monitor
VTRIP level can be selected for either a 5% or 10% supply
with default values of 4.25V or 4.625V. The
HST_3V_MON VTRIP level can be programmed to 2.65V,
2.8V, 2.95V and 3.1V.
The CARD_V_MON thresholds are set in relation to their
corresponding host voltage monitor thresholds. The off-
set can either be +50mV or -50mV. This allows the
designer to select (+50mV) if they want a collapse in the
backend voltage to trigger a local reset condition prior to
the host supply collapsing and powering down the board
without warning. Alternatively they can choose (-50mV) to
trigger a board shutdown based on the host power supply
falling out of spec.
Over-current Circuit Breaker
The SMH4042 provides a circuit breaker function to
protect against short circuit conditions or exceeding the
supply limits. By placing a series resistor between the host
supply and the CBI pins, the breakers will trip whenever
the voltage drop across the series resistor is greater than
50mV for more than 16µs.
The over-current detection circuit was designed to maxi-
mize protection while minimizing false alarms. The most
critical period of time is during the power-on sequence
when the backend circuits are first being energized. If the
card has a faulty component or shorted traces the time to
shut off should be minimal. However, if the board has
been operational for a long period of time the likelihood of
a catastrophic failure occurring is quite low. Therefore, the
SMH4042 employs two different sampling schemes.
down. This provides an effective response time of 4µs.
During normal operation, after the FETs have been turned
on, the sampling rate will be adjusted to 2µs, thus provid-
ing an effective response time of 16µs.
Reset Control
While in the power sequencing mode, the reset outputs
are the last to be released. When they are released all
conditions of a successful power-up sequence must have
been met.
VCC and HST_3V_MON are at or above their
respective VTRIP levels
+
BD-SEL# inputs are true
+
CARD_3V_MON and CARD_5V_MON inputs are at
or above their respective trip levels
+
PWR_EN input is pulled high
+
PCI_RST# is high
The PCI-RST# input must be high for the reset outputs to
be released. Assuming all of the conditions listed above
have been met and PCI_RST# is high and tPURST has
expired, a low input of greater than 40ns duration on the
PCI_RST# input will initiate a reset cycle. The duration of
the reset cycle will be determined by the PCI_RST# input.
During power-up the device will sample the current every
500ns. If eight consecutive overcurrent conditions are
detected the VGATE outputs will immediately be shut
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