ST72324LXX Datasheet, PDF (92/154 Pages) STMicroelectronics – 3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface

ST72324Lxx
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.9 Clock Deviation Causes
10.5.4.10 Noise Error Causes
The causes which contribute to the total deviation See also description of Noise error in Section
are:
10.5.4.3.
– D_TRA: Deviation due to transmitter error (Local
oscillator error of the transmitter or the trans-
mitter is transmitting at a different baud rate).
– D_QUANT: Error due to the baud rate quantiza-
tion of the receiver.
– D_REC: Deviation of the local oscillator of the
receiver: This deviation can occur during the
reception of one complete SCI message as-
suming that the deviation has been compen-
sated at the beginning of the message.
Start bit
The noise flag (NF) is set during start bit reception
if one of the following conditions occurs:
1. A valid falling edge is not detected. A falling
edge is considered to be valid if the 3 consecu-
tive samples before the falling edge occurs are
detected as '1' and, after the falling edge
occurs, during the sampling of the 16 samples,
if one of the samples numbered 3, 5 or 7 is
detected as a “1”.
– D_TCL: Deviation due to the transmission line
(generally due to the transceivers)
All the deviations of the system should be added
and compared to the SCI clock tolerance:
D_TRA + D_QUANT + D_REC + D_TCL < 3.75%
2. During sampling of the 16 samples, if one of the
samples numbered 8, 9 or 10 is detected as a
“1”.
Therefore, a valid Start Bit must satisfy both the
above conditions to prevent the Noise Flag getting
set.
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.
Figure 53. Bit Sampling in Reception Mode
RDI LINE
Sample
clock
sampled values
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
6/16
7/16
7/16
One bit time
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