ST72324LXX Datasheet, PDF (31/154 Pages) STMicroelectronics – 3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface

ST72324Lxx
INTERRUPTS (Cont’d)
Table 9. Interrupt Mapping
N°
Source
Block
Description
Register
Label
Priority
Order
Exit
from
HALT
Exit
from
Active
HALT
Address
Vector
RESET
TRAP
Reset
Software interrupt
yes
yes FFFEh-FFFFh
N/A
no
no FFFCh-FFFDh
0
Not used
FFFAh-FFFBh
1
MCC/RTC
Main clock controller time base inter-
rupt
MCCSR
Higher
no
yes FFF8h-FFF9h
2
ei0
External interrupt port A3..0
Priority
yes
yes¹⁾ FFF6h-FFF7h
3
ei1
External interrupt port F2..0
N/A
4
ei2
External interrupt port B3..0
yes yes¹⁾ FFF4h-FFF5h
yes yes¹⁾ FFF2h-FFF3h
5
ei3
External interrupt port B7..4
yes yes¹⁾ FFF0h-FFF1h
6
Not used
7
SPI
SPI peripheral interrupts
SPICSR
FFEEh-FFEFh
yes yes¹⁾ FFECh-FFEDh
8
TIMER A TIMER A peripheral interrupts
TASR
no
no FFEAh-FFEBh
9
TIMER B TIMER B peripheral interrupts
TBSR
no
no FFE8h-FFE9h
10
SCI
SCI Peripheral interrupts
SCISR
Lower
Priority
no
no FFE6h-FFE7h
Notes:
1. Valid for ROM devices. For Flash devices only a RESET or MCC/RTC interrupt can be used to wake-
up from Active Halt mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure 18). This control allows to have up to 4 fully
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
■ Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared when disabling
these interrupts by setting their I0_x and I1_x in
the matching ISPR
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