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| STM32F103ZEH7 Datasheet, PDF (91/130 Pages) STMicroelectronics – High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces | |||
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STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
5.3.15
Figure 46. I/O AC characteristics definition
90%
50%
10%
10%
50%
90%
EXT ERNAL
O UTP UT
ON 50pF
tr(I O)out
tr(I O)out
T
Maximum fr equency is achieved if (tr + tf) ⤠2/3) T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 46).
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 10.
Table 49. NRST pin characteristics
Symbol
Parameter
Conditions Min Typ Max Unit
VIL(NRST)(1) NRST Input low level voltage
VIH(NRST)(1) NRST Input high level voltage
â0.5
2
0.8
V
VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
200
mV
RPU
Weak pull-up equivalent resistor(2)
VF(NRST)(1) NRST Input filtered pulse
VNF(NRST)(1) NRST Input not filtered pulse
VIN = VSS
30 40
300
50
kΩ
100 ns
ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
. to the series resistance must be minimum (~10% order)
Figure 47. Recommended NRST pin protection
External
reset circuit(1)
VDD
NRST(2)
RPU
0.1 µF
Internal Reset
Filter
STM32F10xxx
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 49. Otherwise the reset will not be taken into account by the device.
Doc ID 14611 Rev 8
91/130
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