PSD4235G2V_09 Datasheet, PDF (91/124 Pages) STMicroelectronics – Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)

PSD4235G2V
Power management
Figure 31. APD unit
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
ALE
RESET
CSI
CLKIN
EDGE
DETECT
CLR PD
APD
COUNTER
PD
DISABLE BUS
INTERFACE
Secondary Flash
Memory Select
Primary Flash
Memory Select
PLD _{SRAM Select}
POWER DOWN
(PDN) Select
DISABLE Primary and Secondary
FLASH Memory and SRAM
AI04939
Table 48. PSD timing and standby current during Power-down mode⁽¹⁾
Mode
PLD propagation
delay
Memory Access recovery time to Typical standby
access time
normal access
current
Power-
down
Normal t_PD
No Access
t_LVDV
I_SB(2)
1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the
Turbo bit.
2. Typical current consumption, see Table 60, assuming no PLD inputs are changing state and the PLD
Turbo bit is 0.
20.3
Other power saving options
The PSD offers other reduced power saving options that are independent of the Power-
down mode. Except for PSD Chip Select input (CSI, PD2) features, they are enabled by
setting bits in PMMR0 and PMMR2 (as summarized in Section 5.15 and Table 23).
20.4
PLD power management
The power and speed of the PLDs are controlled by the Turbo bit (Bit 3) in PMMR0. By
setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified standby
current when the inputs are not switching for an extended time of 70 ns. The propagation
delay time is increased after the Turbo bit is set to ’1’ (turned off) when the inputs change at
a composite frequency of less than 15 MHz. When the Turbo bit is reset to ’0’ (turned on),
the PLDs run at full power and speed. The Turbo bit affects the PLD’s DC power, AC power,
and propagation delay. See the AC and DC characteristics tables for PLD timing values
(seeTable 68).
Blocking MCU control signals with the PMMR2 bits can further reduce PLD AC power
consumption.
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