STM32F401XB Datasheet, PDF (90/135 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 105 DMIPS, 256KB Flash/64KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces

STM32F401xB STM32F401xC
Electrical characteristics
Table 54. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FT and NRST I/O input
hysteresis
1.7 V≤V_DD≤3.6 V
-
10%
V_DD(3)
-
V
V_HYS
BOOT0 I/O input hysteresis
1.75 V≤V_DD ≤3.6 V,
-40 °C≤T_A ≤105 °C
-
100
1.7 V≤V_DD ≤3.6 V,
0 °C≤T_A ≤105 °C
-
mV
I/O input leakage current ⁽⁴⁾
I_{lkg I/O FT input leakage current (5)}
V_SS ≤V_IN ≤V_DD
V_IN = 5 V
-
-
-
-
±1
µA
3
Weak pull-up
R_PU
equivalent
resistor⁽⁶⁾
All pins
except for
PA10
(OTG_FS_ID
)
PA10
(OTG_FS_ID
)
All pins
except for
PA10
Weak pull-down _{(OTG_FS_ID}
R_PD
equivalent
resistor⁽⁷⁾
)
PA10
(OTG_FS_ID
)
V_IN = V_SS
V_IN = V_DD
30
40
50
7
10
30
40
14
kΩ
50
7
10
14
C_IO(8) I/O pin capacitance
-
-
5
-
pF
1. Guaranteed by design.
2. Guaranteed by test in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 53: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 53: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 30.
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