STW81200 Datasheet, PDF (9/58 Pages) STMicroelectronics – Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs

STW81200
Pin No
Name
22 LD_SDO
23 SDI
24 SCK
25 LE
26 VDD_DSM_NDIV
27 VREG_DIG
28 VIN_LDO_RF_DIG
29 VREG_RF
30 RF1_OUTN
31 RF1_OUTP
32 VCC_RFOUT
33 RF2_OUTN
34 RF2_OUTP
35 TEST_SE
36 VIN_LDO_4V5
Pin definitions
Table 2. Pin description (continued)
Description
Observation
Lock Detector/SPI Data output
CMOS push-pull Output 2.5V with slew
rate control or open drain (1.8V to 3.3V
tolerant)
SPI Data input
CMOS Schmitt triggered Input, 1.8 V
compatible, 3.3 V tolerant
SPI clock
CMOS Schmitt triggered Input, 1.8 V
compatible, 3.3 V tolerant
SPI load enable
CMOS Schmitt triggered Input, 1.8 V
compatible, 3.3 V tolerant
Supply voltage for DSM and N
divider
This pin must be connected to
VREG_DIG
Regulated output voltage for
digital circuitry regulator
-
Supply voltage for RF Output
divider stage and digital regulators
-
Regulated output voltage for RF
Output Divider stage regulator
-
Main RF negative output
Main RF positive output
Supply voltage for RF Output
stages
50 Ω output impedance
50 Ω output impedance
Connected to VREG_DIV, VREG_4V5
or external 5V
Auxiliary RF negative output
Auxiliary RF positive output
Test pin
50 Ω output impedance
50 Ω output impedance
This pin must be connected to ground
Supply voltage for 4.5 V regulator -
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