STW81200 Datasheet, PDF(41/58 Page) STMicroelectronics – Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs

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STW81200 Datasheet, PDF (41/58 Pages) STMicroelectronics – Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs

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STW81200

Circuit description

[14] PLL_MUX_DIV: PLL MUX setting; select the desired signal path from VCO to the N Divider

(VCO divider in the PLL feedback path):

0: VCO direct to N Divider (default)

1: VCO divided to N Divider (division ratio set by RF1_DIV_SEL in register ST1)

[13:12] CP_SUPPLY_MODE: Charge Pump supply mode settings; value to be set according to the

supply used for charge pump core circuit (pin #16)

00: (0) 4.5V to 5.0 V

01: (1) 3.3 V

10: (2) 2.6 V

11: (3) Reserved

[11] KVCO_COMP_DIS: disable KVCO compensation circuit

0: compensation enabled (default - CP current auto-adjusted to compensate KVCO variation)

1: compensation disabled (CP current fixed by CP_SEL settings)

[10] PFD_POL: set PFD polarity

0: standard mode (default)

1: âinvertedâ mode (to be used only with active inverting loop filter or with VCO with negative

tuning characteristics)

[9:8] REF_BUFF_MODE: set Reference Clock buffer mode

00: (0) Reserved

01: (1) Differential Mode (Ref. clock signal on pin #20 and #21)

10: (2) XTAL Mode (Xtal oscillator enabled with crystal connected on pin #20 and #21)

11: (3) Single Ended Mode (Ref. clock signal on pin #21)

[7] MUTE_LOCK_EN: enables mute function

0: âmute on unlockâ function disabled

1: âmute on unlockâ function enabled (RF output stages are put OFF when PLL is unlocked)

[6] LD_ACTIVELOW: set low state as lock indicator

0: set lock indicator active high (LD=0 means PLL unlocked; LD=1 means PLL locked)

1: set lock indicator active low (LD=0 means PLL locked; LD=1 means PLL unlocked)

[5:3] LD_PREC: set Lock Detector precision

000: (0) 2 ns (default for Integer Mode)

001: (1) 4 ns (default for Fractional Mode)

010: (2) 6 ns

011: (3) 8 ns

100: (4) 10 ns

101: (5) 12 ns

110: (6) 14 ns

111: (7) 16 ns

[2:0] LD_COUNT: set Lock Detector counter for lock condition

000: (0) 4

001: (1) 8 (default for FPFD ~1MHz in Integer Mode)

010: (2) 16

011: (3) 64

100: (4) 256

101: (5) 1024 (default for FPFD ~50MHz in both Fractional/Integer Mode)

110: (6) 2048

111: (7) 4096

DocID025943 Rev 7

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