STD70N02L_07 Datasheet, PDF (9/17 Pages) STMicroelectronics – N-channel 25V - 0.0068Ω - 60A - DPAK - IPAK STripFET™ III Power MOSFET

STD70N02L - STD70N02L-1
Appendix A Buck convert
Figure 15. Synchronous buck converter
Buck convert
The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the wotking
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is removed to allow for a safer working junction
temperature.
The low side (SW2) device requires:
Very low R_DS(on) to reduce conduction losses
Small Q_gls to reduce the gate charge losses
Small C_oss to reduce losses due to output capacitance
Small Q_rr to reduce losses on SW1 during its turn-on
The C_gd/C_gs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to
avoid the cross conduction phenomenon.
The high side (SW1) device requires:
Small R_G and L_G to allow higher gate current peak and to limit the voltage feedback on the
gate
Small Q_g to have a faster commutation and to reduce gate charge losses
Low R_DS(on) to reduce the conduction losses
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