M93S46-W Datasheet, PDF (9/32 Pages) STMicroelectronics – 4 Kbit, 2 Kbit and 1 Kbit serial MICROWIRE bus EEPROM with write protection

M93S46-W M93S56-W M93S66­W
Clock pulse counter
4
Clock pulse counter
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater
than the number delivered by the Bus Master (the micro- controller). This can lead to a
misalignment of the instruction of one or more bits (as shown in Figure 3: "Write sequence
with one clock glitch".) and may lead to the writing of erroneous data at an erroneous
address.
To combat this problem, the M93Sx6 has an on­chip counter that counts the clock pulses
from the start bit until the falling edge of the Chip Select Input (S). If the number of clock
pulses received is not the number expected, the WRITE, PAWRITE, WRALL, PRWRITE or
PRCLEAR instruction isaborted, and the contents of the memory are not modified.
The number of clock cycles expected for each in- struction, and for each member of the
M93Sx6 family, are summarized in Table 2: "Instruction set for the M93S46" and Table 3:
"Instruction set for the M93S66, M93S56". For example, a Write Data to Memory (WRITE)
instruction on the M93S56 (or M93S66) expects 27 clock cycles from the start bit to the
falling edge of Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 8 Address bits
+ 16 Data bits
Figure 3: Write sequence with one clock glitch
S
C
D
START "0"
"1"
WRITE
An
An-1
An-2
Glitch
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
AI01395B
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