M93S46-W Datasheet, PDF (12/32 Pages) STMicroelectronics – 4 Kbit, 2 Kbit and 1 Kbit serial MICROWIRE bus EEPROM with write protection

Instructions
Instruction Description
PREN
PRDS
Protection
Register
Enable
Protection
Register
Disable
Start Op-
W PRE
bit code
Address
(1)(2)
11
1
00 11XXXXXX
11
1
00 00000000
M93S46-W M93S56-W M93S66­W
Data
Required
clock
cycles
Additional
comments
-
11
-
-
11
OTP bit is set
permanently
Notes:
(1)_{Address bit A7 is not decoded by the M93S56.}
(2)_{X = Don’t Care bit.}
5.1
Read
The Read Data from Memory (READ) instruction outputs serial data on Serial Data Output
(Q). When the instruction is received, the op-code and address are decoded, and the data
from the memory is transferred to an output shift register. A dummy 0 bit is output first,
followed by the 16-bit word, with the most significant bit first. Output data changes are
triggered by the rising edge of Serial Clock (C). The M93Sx6 automatically increments the
internal address counter and clocks out the next byte (or word) as long as the Chip Select
Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words)
and a continuous stream of data can be read.
5.2
Write enable and write disable
The Write Enable (WEN) instruction enables the future execution of write instructions, and
the Write Disable (WDS) instruction disables it. When power is first applied, the M93Sx6
initializes itself so that write instructions are disabled. After a Write Enable (WEN)
instruction has been executed, writing remains enabled until an Write Disable (WDS)
instruction is executed, or until VCC falls below the power-on reset threshold voltage. To
protect the memory contents from accidental corruption, it is advisable to issue the Write
Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ)
instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions.
Figure 4: READ sequence
READ
PRE
S
D
1 1 0 An A0
Q
Qn
Q0
ADDR
OP
CODE
DATA OUT
MSv36051V1
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