M440T1MV Datasheet, PDF (9/26 Pages) STMicroelectronics – 3.3V, 32 Mbit (1024 Kbit x 32) TIMEKEEPER SRAM

M440T1MV
Table 3. Clock Operating Modes
Mode
V_CC
EC
GC
WC
Deselect
V_IH
X
X
WRITE
V_IL
X
V_IL
2.97 to 3.6V
READ
V_IL
V_IL
V_IH
READ
V_IL
V_IH
V_IH
Deselect
V_SO to
V_PFD(min)⁽¹⁾
X
X
X
Deselect
≤ V_SO(1)
X
X
X
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 12., page 20 for details.
DQC0 - 7
Hi-Z
D_IN
D_OUT
Hi-Z
Hi-Z
Hi-Z
Figure 6. Memory READ Mode AC Waveforms, Chip Enable- or Output Enable-Controlled
A0-A19
E1 - E4
G
DQ0-DQ31
tAVAV
VALID
tAVQV
tELQV
tELQX
tGLQV
tGLQX
tAXQX
tEHQZ
tGHQZ
DATA OUT
AI05606
Figure 7. Memory READ Mode AC Waveforms, Address-Controlled
A0-A19
tAVAV
VALID
tAXQX
tAVQV
DQ0-DQ31
DATA VALID
DATA VALID
AI05607
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