M440T1MV Datasheet, PDF (8/26 Pages) STMicroelectronics – 3.3V, 32 Mbit (1024 Kbit x 32) TIMEKEEPER SRAM

M440T1MV
OPERATION MODES
Memory READ Mode
The M440T1MV is in the 32-bit READ Mode when-
ever W1 - W4 (WRITE Enable Byte 1 to 4) are high
and E1 - E4 - Chip Enable Bytes 1 to 4 are low
(see Table 2., page 8). The unique address spec-
ified by the 20 address inputs defines which one of
the 1,048,576 long words of data is to be access-
ed. Valid data will be available at the Data I/O pins
within Address Access Time (t_AVQV) after the last
address input signal is stable, providing the E1-4
and G access times are also satisfied. If the E1-4
and G access times are not met, valid data will be
available after the latter of the Chip Enable Access
Times (t_ELQV) or Output Enable Access Time
(t_GLQV).
The state of the thirty-two three-state Data I/O sig-
nals is controlled by E1-4 and G. If the outputs are
activated before t_AVQV, the data lines will be driven
to an indeterminate state until t_AVQV. If the Ad-
dress Inputs are changed while E1-4 and G re-
main active, output data will remain valid for
Output Data Hold Time (t_AXQX) but will go indeter-
minate until the next Address Access.
Clock READ Mode
The clock is in the READ Mode whenever WC
(Clock WRITE Enable) is high and EC (Clock Chip
Enable) is low. The unique address specified by
the 6 Address Inputs defines which one of the 64
bytes of clock data is to be accessed. Valid data
will be available at the Data I/O pins (DQC0-7)
within Address Access Time (t_AVQV) after the last
address input signal is stable, providing the EC
and GC access times are also satisfied. If the EC
and GC access times are not met, valid data will
be available after the latter of the Chip Enable Ac-
cess Times (t_ELQV) or Output Enable Access Time
(t_GLQV).
The state of the eight three-state Data I/O signals
is controlled by EC and G. If the outputs are acti-
vated before t_AVQV, the data lines will be driven to
an indeterminate state until t_AVQV. If the Address
Inputs are changed while EC and G remain active,
output data will remain valid for Output Data Hold
Time (t_AXQX) but will go indeterminate until the
next Address Access. See section on Reading and
Setting the Clock under CLOCK OPERATION for
more details.
Table 2. Memory Operating Modes
Mode
V_CC
E4 E3 E2 E1
G
W4
W3
W2
W1
DQ24- DQ16- DQ8-
DQ31 DQ23 DQ15
DQ0-
DQ7
Power
Byte WRITE
H H H L H X X X L Hi-Z Hi-Z Hi-Z DIN Active
Byte WRITE
H H L H H X X L X Hi-Z Hi-Z DIN Hi-Z Active
Byte WRITE
H L H H H X L X X Hi-Z DIN Hi-Z Hi-Z Active
Byte WRITE
L H H H H L X X X DIN Hi-Z Hi-Z Hi-Z Active
Byte WRITE
X X X L H H H H L Hi-Z Hi-Z Hi-Z DIN Active
Byte WRITE
X X L X H H H L H Hi-Z Hi-Z DIN Hi-Z Active
Byte WRITE
X L X X H H L H H Hi-Z DIN Hi-Z Hi-Z Active
Byte WRITE
L X X X H L H H H DIN Hi-Z Hi-Z Hi-Z Active
Long Word
WRITE
2.97 to 3.6V
L
L
L
L
H
L
L
L
L
D_IN
D_IN
D_IN
D_IN Active
Byte READ
H H H L L X X X H Hi-Z Hi-Z Hi-Z DOUT Active
Byte READ
H H L H L X X H X Hi-Z Hi-Z DOUT Hi-Z Active
Byte READ
H L H H L X H X X Hi-Z DOUT Hi-Z Hi-Z Active
Byte READ
L H H H L H X X X DOUT Hi-Z Hi-Z Hi-Z Active
Long Word
READ
L L L L L H H H H DOUT DOUT DOUT DOUT Active
Deselect
H H H H X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Stdby
Deselect
V_SO to
V_PFD(min)⁽¹⁾
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CMOS
Standby
Deselect
≤ V_SO(1)
Battery
X X X X X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Back-up
Mode
Note: X = V_IH or V_IL; V_SO = Battery Back-up Switchover Voltage.
1. See Table 12., page 20 for details.
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