STM32F103XC Datasheet, PDF (89/118 Pages) STMicroelectronics – Performance line, ARM-based 32-bit MCU with up to 512 KB Flash, USB, CAN, 11 timers, 3 ADCs and 13 communication interfaces

STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
5.3.16
Communications interfaces
I²C interface characteristics
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under ambient temperature, f_PCLK1 frequency and V_DD supply voltage conditions
summarized in Table 9.
The STM32F103xC performance line I²C interface meets the requirements of the standard
I²C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V_DD is disabled, but is still present.
The I²C characteristics are described in Table 49. Refer also to Section 5.3.13: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 49. I²C characteristics
Symbol
Parameter
Standard mode I²C⁽¹⁾ Fast mode I²C⁽¹⁾⁽²⁾
Min
Max
Min
Max
Unit
t_w(SCLL)
t_w(SCLH)
t_su(SDA)
t_h(SDA)
t_r(SDA)
t_r(SCL)
t_f(SDA)
t_f(SCL)
t_h(STA)
t_su(STA)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
4.7
1.3
µs
4.0
0.6
250
100
0⁽³⁾
0⁽⁴⁾
900⁽³⁾
1000 20 + 0.1C_b 300
ns
300 20 + 0.1C_b 300
4.0
0.6
µs
4.7
0.6
t_su(STO) Stop condition setup time
4.0
t_w(STO:STA)
Stop to Start condition time
(bus free)
4.7
0.6
μs
1.3
μs
C_b
Capacitive load for each bus
line
400
400
pF
1. Values based on standard I²C protocol requirement, not tested in production.
2.
f_PCLK1
higher
must be higher than 2 MHz to achieve the maximum standard mode
than 4 MHz to achieve the maximum fast mode I²C frequency.
I²C
frequency.
It
must
be
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
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