STM32F372VBT6 Datasheet, PDF (85/131 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, up to 256KB Flash+32KB SRAM

STM32F37xxx
Electrical characteristics
Note:
I/O pins are powered from V_DD voltage except pins which can be used as SDADC inputs:
- The PB2, PB10 and PE7 to PE15 I/O pins are powered from V_DDSD12.
- PB14 to PB15 and PD8 to PD15 I/O pins are powered from V_DDSD3. All I/O pin ground is
internally connected to V_SS.
V_DD mentioned in the Table 52 represents power voltage for a given I/O pin (V_DD or
V_DDSD12 or V_DDSD3).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 17 and Figure 18 for standard I/Os, and
in Figure 19 and Figure 20 for 5 V tolerant I/Os.
Figure 17. TC and TTa I/O input characteristics - CMOS port
V_IL/V_IH (V)
V_IHmin 2.0
1.3
V_ILmax 0.7
0.6
Tested ^{in production}
Area not determined
Tested ^{in production}
2.0
CMOS ^{standard requirements VIHmin = 0.7 VDD}
VBIHm_aⁱ_sⁿ_{e=d0o.4n4d5eVs}^{DigD+n0s.i3m9u8lations}
VBILm_a^a_s^x_e=d0o.n3Vd^{DeDs+ig0n.0s7imulations}
CMOS standard requirements VILmax = 0.3VDD
V_DD (V)
2.7
3.0
3.3
3.6
MS30255V2
V_IL/V_IH (V)
V_IHmin 2.0
1.3
0.8
V_ILmax 0.7
Figure 18. TC and TTa I/O input characteristics - TTL port
Area not determined
TTL standard requirements VIHmin = 2 V _{VBIHmaisne=d0o.4n4d5eVs}^D_ig^{D+n0s.i3m9u8lations}
VIL_B^m_a^ax_s=ed0.o3nVd^{DeD+si0g.n07simulations}
TTL standard requirements VILmax = 0.8 V
V_DD (V)
2.0
2.7
3.0
3.3
3.6
MS30256V4
DocID022691 Rev 4
85/131
114