STM32L100RC Datasheet, PDF (84/104 Pages) STMicroelectronics – Reset and supply management

Electrical characteristics
STM32L100RC
Note:
Table 51. USB: full speed electrical characteristics (continued)
Driver characteristics⁽¹⁾
Symbol
Parameter
Conditions
Min
Max
Unit
t_rfm
Rise/ fall time matching
t_r/t_f
90
110
%
V_CRS Output signal crossover voltage
1.3
2.0
V
1. Guaranteed by design, not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
I2S characteristics
Table 52. I2S characteristics
Symbol
Parameter
Conditions
Min
Max Unit
f_MCK
f_CK
I2S Main Clock Output
I2S clock frequency
Master data: 32 bits
Slave data: 32 bits
256 x 8K 256xFs ⁽¹⁾ MHz
-
64xFs
MHz
-
64xFs
D_CK I2S clock frequency duty cycle Slave receiver, 48KHz
30
t_r(CK)
t_f(CK)
I2S clock rise time
I2S clock fall time
Capacitive load CL=30pF
-
t_v(WS) WS valid time
Master mode
4
t_h(WS) WS hold time
Master mode
0
t_su(WS) WS setup time
Slave mode
15
t_h(WS) WS hold time
Slave mode
0
t_{su(SD_MR)} Data input setup time
Master receiver
8
t_{su(SD_SR)} Data input setup time
Slave receiver
9
t_{h(SD_MR) Data input hold time}
Master receiver
5
t_{h(SD_SR)}
Slave receiver
4
t_{v(SD_ST)} Data output valid time
Slave transmitter
(after enable edge)
-
70
%
8
8
24
-
-
-
-
-
-
ns
-
64
t_{h(SD_ST)} Data output hold time
Slave transmitter
(after enable edge)
22
-
t_{v(SD_MT)} Data output valid time
Master transmitter
(after enable edge)
-
12
t_{h(SD_MT)} Data output hold time
Master transmitter
(after enable edge)
8
-
1. The maximum for 256xFs is 8 MHz
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), f_MCK, f_CK and D_CK values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
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