RM0313 Datasheet, PDF (84/900 Pages) STMicroelectronics – This reference manual targets application developers

Power control (PWR)
RM0313
6.3.2
6.3.3
Peripheral clock gating
In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped
at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB peripheral clock enable register
(RCC_AHBENR)
Low power modes
Entering low power mode
Low power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or
WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex^®-M4 with
FPU System Control register is set on Return from ISR.
Exiting low power mode
From Sleep modes, and Stop modes the MCU exit low power mode depending on the way
the low power mode was entered:
• If the WFI instruction or Return from ISR was used to enter the low power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
• If the WFE instruction is used to enter the low power mode, the MCU exits the low
power mode as soon as an event occurs. The wakeup event can be generated either
by:
– NVIC IRQ interrupt.
- When SEVONPEND = 0 in the Cortex^®-M4 with FPU System Control register. By
enabling an interrupt in the peripheral control register and in the NVIC. When the
MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC
peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register)
have to be cleared.
Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
- When SEVONPEND = 1 in the Cortex^®-M4 with FPU System Control register.
By enabling an interrupt in the peripheral control register and optionally in the
NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and
when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt
clear pending register) have to be cleared.
All NVIC interrupts will wakeup the MCU, even the disabled ones. Only enabled
NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
– Event
Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is
not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ
channel pending bit as the pending bits corresponding to the event line is not set.
It may be necessary to clear the interrupt flag in the peripheral.
From Standby mode the MCU exit low power mode through an external reset (NRST pin),
an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs
(see Figure 165: RTC block diagrams).
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