RM0313 Datasheet, PDF (501/900 Pages) STMicroelectronics – This reference manual targets application developers

RM0313
System window watchdog (WWDG)
Note:
22.3.4
In some applications, the EWI interrupt can be used to manage a software system check
and/or system recovery/graceful degradation, without generating a WWDG reset. In this
case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to
avoid the WWDG reset, then trigger the required actions.
The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task,
the WWDG reset will eventually be generated.
How to program the watchdog timeout
You can use the formula in Figure 164 to calculate the WWDG timeout.
Warning: When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
Figure 164. Window watchdog timing diagram
4;=#.4DOWNCOUNTER
7;=
X&
2EFRESHNOTALLOWED 2EFRESHALLOWED
4BIT
4IME
2%3%4
AIC
The formula to calculate the timeout value is given by:
t_WWDG = t_PCLK1 × 4096 × 2WDGTB[1:0] × (T[5:0] + 1)
(ms)
where:
t_WWDG: WWDG timeout
t_PCLK: APB1 clock period measured in ms
4096: value corresponding to internal divider
As an example, lets assume APB1 frequency is equal to 48 MHz, WDGTB[1:0] is set to 3
and T[5:0] is set to 63:
tWWDG = 1 ⁄ 48000 × 4096 × 23 × (63 + 1) = 43.69 ms
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