PSD813F1V Datasheet, PDF (84/110 Pages) STMicroelectronics – Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 3.3V

PSD813F1V
Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices)
Symbol
Parameter
Conditions
-15
-20
Min Max Min Max
PT
Aloc
Maximum Frequency
External Feedback
1/(t_S+t_CO)
17.8
14.7
f_MAX
Maximum Frequency
Internal Feedback (f_CNT)
1/(t_S+t_CO–10)
19.6
17.2
Maximum Frequency
Pipelined Data
1/(t_CH+t_CL)
33.3
31.2
t_S
Input Setup Time
27
35
+4
t_H
Input Hold Time
0
0
t_CH
Clock High Time
Clock Input 15
16
t_CL
Clock Low Time
Clock Input 15
16
t_CO
Clock to Output Delay
Clock Input
35
39
t_ARD
CPLD Array Delay
Any macrocell
29
33 + 4
t_MIN
Minimum Clock Period²
t_CH+t_CL
29
32
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0.
2. CLKIN (PD1) tCLCL = tCH + tCL.
Turbo
Off
Slew
rate¹
Unit
MHz
MHz
+ 20
MHz
ns
ns
ns
ns
– 6 ns
ns
ns
Figure 44. Asynchronous Reset / Preset
tARPW
RESET/PRESET
INPUT
REGISTER
OUTPUT
tARP
AI02864
Figure 45. Asynchronous Clock Mode Timing (Product Term Clock)
tCHA
tCLA
CLOCK
tSA tHA
INPUT
REGISTERED
OUTPUT
tCOA
AI02859
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