M58LT256JST Datasheet, PDF (84/106 Pages) STMicroelectronics – 256 Mbit (16 Mb × 16, multiple bank, multilevel, burst) 1.8 V supply, secure Flash memories

Common Flash Interface
M58LT256JST, M58LT256JSB
Table 43. Bank and Erase block region 1 information (continued)
M58LT256JST
Offset
Data
M58LT256JSB
Offset
Data
Description
(P+30)h = 13Ah 02h
(P+30)h = 13Ah
Bank region 1 (Erase Block type 1): bits per cell,
internal ECC
02h ^{Bits 0-3: bits per cell in erase region}
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
(P+31)h = 13Bh 03h
(P+31)h = 13Bh
Bank region 1 (Erase Block type 1): page mode
and synchronous mode capabilities
Bit 0: page-mode reads permitted
03h _{Bit 1: synchronous reads permitted}
Bit 2: synchronous writes permitted
Bits 3-7: reserved
(P+32)h = 13Ch 0Eh Bank region 1 Erase Block type 2 information
(P+33)h = 13Dh 00h Bits 0-15: n+1 = number of identical-sized
(P+34)h = 13Eh 00h ^{erase blocks}
Bits 16-31: n × 256 = number of bytes in erase
(P+35)h = 13Fh 02h _{block region}
(P+36)h = 140h 64h _{Bank region 1 (Erase Block type 2)}
(P+37)h = 141h 00h ^{Minimum block erase cycles × 1000}
(P+38)h = 142h
Bank regions 1 (Erase Block Type 2): bits per cell,
internal ECC
02h Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
(P+39)h = 143h
Bank region 1 (Erase Block Type 2): page mode
and synchronous mode capabilities
Bit 0: page-mode reads permitted
03h _{Bit 1: synchronous reads permitted}
Bit 2: synchronous writes permitted
Bits 3-7: reserved
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Tables 29 to 34.
3. Although the device supports Page Read mode, this is not described in the datasheet as its use is not
advantageous in a multiplexed device.
84/106