ST10F269ZX Datasheet, PDF (83/184 Pages) STMicroelectronics – 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM

ST10F269
12 - PARALLEL PORTS
DP6.y
Port Direction Register DP6 Bit y
DP6.y = 0: Port line P6.y is an input (high impedance)
DP6.y = 1: Port line P6.y is an output
ODP6 (F1CEH / E7H)
15 14 13 12 11 10 9
-------
ESFR
Reset Value: --00h
8
7
6
5
4
3
2
1
0
- ODP6.7 ODP6.6 ODP6.5 ODP6.4 ODP6.3 ODP6.2 ODP6.1 ODP6.0
RW RW RW RW RW RW RW RW
ODP6.y
Port 6 Open Drain Control Register Bit y
ODP6.y = 0: Port line P6.y output driver in push-pull mode
ODP6.y = 1: Port line P6.y output driver in open drain mode
12.9.1 - Alternate Functions of Port 6
A programmable number of chip select signals (CS4...CS0) derived from the bus control registers
(BUSCON4...BUSCON0) can be output on 5 pins of Port 6.
The number of chip select signals is selected via PORT0 during reset. The selected value can be read
from bit-field CSSEL in register RP0H (read only) in order to check the configuration during run time.
The Table 23 summarizes the alternate functions of Port 6 depending on the number of selected chip
select lines (coded via bit-field CSSEL).
Table 23 : Port 6 Alternate Functions
Port 6
Alternate Function
CSSEL = 10
Alternate Function
CSSEL = 01
Alternate Function
CSSEL = 00
Alternate Function
CSSEL = 11
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
Chip select CS0
Chip select CS1
General purpose I/O
General purpose I/O
General purpose I/O
HOLD External hold request input
HLDA Hold acknowledge output
BREQ Bus request output
Chip select CS0
Chip select CS1
Chip select CS2
General purpose I/O
General purpose I/O
Chip select CS0
Chip select CS1
Chip select CS2
Chip select CS3
Chip select CS4
Figure 36 : Port 6 I/O and Alternate Functions
Alternate Function
a)
Port 6
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
General Purpose Input/Output
BREQ
HLDA
HOLD
CS4
CS3
CS2
CS1
CS0
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