ST10F269ZX Datasheet, PDF (119/184 Pages) STMicroelectronics – 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM

ST10F269
18 - SYSTEM RESET
Depending on the delay of the next applied reset,
the MCU can enter a synchronous reset or an
asynchronous reset. If RPD pin is below 2.5V an
asynchronous reset starts, if RPD pin is above
2.5V a synchronous reset starts. (See Section
18.1 - and Section 18.2 -).
Note that an internal pull-down is connected to
RPD pin and can drive a 100µA to 200µA current.
This Pull-down is turned on when RSTIN pin is
low.
To properly use the bidirectional reset features,
the schematic (or equivalent) of Figure 60 must be
implemented. R1-C1 only work for power-on or
manual reset in the same way as explained
previously. D1 diode brings a faster discharge of
Figure 58 : Internal (simplified) Reset Circuitry.
EINIT Instruction
Clr
Q
Set
C1 capacitor at power-off during repetitive
switch-on / switch-off sequences. D2 diode
performs an OR-wired connection, it can be
replaced with an open drain buffer. R2 resistor
may be added to increase the pull-up current to
the open drain in order to get a faster rise time on
RSTIN pin when bidirectional function is activated.
The start-up configurations and some system
features are selected on reset sequences as
described in Table 38 and Table 39.
Table 38 describes what is the system
configuration latched on PORT0 in the five
different reset ways. Table 39 summarizes the
state of bits of PORT0 latched in RP0H,
SYSCON, BUSCON0 registers.
RSTOUT
Reset State
Machine
Clock
V_DD
Internal
Reset
Signal
Trigger
SRST instruction
watchdog overflow
Clr
Reset Sequence
BDRSTEN
(512 CPU Clock Cycles)
RSTIN
Asynchronous
Reset
From/to Exit
Powerdown
Circuit
V_DD
RPD
Weak pull-down
(~200µA)
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