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STM8AF526X Datasheet, PDF (81/125 Pages) STMicroelectronics – Automotive 8-bit MCU, with up to 128 Kbyte Flash, data EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 to 5.5 V
STM8AF526x/8x/Ax STM8AF6269/8x/Ax
Electrical characteristics
10.3.9
SPI interface
Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under ambient temperature, fMASTER frequency, and VDD supply voltage
conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 41. SPI characteristics
Symbol
Parameter
Conditions
Min
Max Unit
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
tsu(NSS)(3)
th(NSS)(3)
ttww((SSCCKKHL))((33))
ttssuu((MSII))((33))
SPI clock frequency
Master mode
Slave mode
0
VDD < 4.5 V
0
VDD = 4.5 V to 5.5 V
0
SPI clock rise and fall time Capacitive load: C = 30 pF
-
NSS setup time
NSS hold time
Slave mode
Slave mode
4 * tMASTER
70
SCK high and low time
Data input setup time
Master mode
Master mode
Slave mode
tSCK/2 - 15
tSCK/2 + 15
5
5
10
6(1)
8(1)
25(2)
-
-
ttww((SSCCKKHL))((33))
-
-
MHz
tthh((MSII))((33))
Data input hold time
Master mode
Slave mode
7
10
ta(SO)(3)(4) Data output access time Slave mode
-
tdis(SO)(3)(5) Data output disable time Slave mode
25
tv(SO)(3) Data output valid time
Slave mode
VDD < 4.5 V
(after enable edge) VDD = 4.5 V to 5.5 V
-
-
tv(MO)(3) Data output valid time
Master mode (after enable edge)
-
th(SO)(3)
th(MO)(3)
Data output hold time
Slave mode (after enable edge)
Master mode (after enable edge)
31
12
-
ns
-
3* tMASTER
75
53
30
-
-
1. fSCK < fMASTER/2.
2. The pad has to be configured accordingly (fast mode).
3. Guaranteed by design or by characterization results, not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
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