VS6552 Datasheet, PDF (8/26 Pages) STMicroelectronics – VGA Color CMOS Image Sensor Module

VS6552
Figure 3. VS6552 Power-up Sequence
Standby
Sleep Clock active
Idle
VDD (1.8V)
AVDD (2.8V)
PDN
CLK
PCLKP/N
PDATAP/N
MSDA
MSCL
Streaming
Mode Change: Sleep -> Clock active Mode Change: Clock active -> Idle
and enable data qualification clock and
general configuration
Mode Command: Idle -> Streaming
also enable data output
3.4.2 Active Signals with Unpowered VS6552
All signals going into the VS6552 must be either at
a low state or high impedance when power is re-
moved from the device. The exceptions to this rule
are the I²C lines which may be at a low or high
state and the clock which can be active.
3.5 Clock and Frame Rate Timing
3.5.1 Video Frame Rate Control
The output frame rate of VS6552 can be reduced
by extending the frame length. The extension is
achieved by adding 'blank' video lines to act as
timing padding. This is advantageous as it does
not reduce the pixel readout rate and therefore
does not introduce unwanted motion distribution
effects to the image. The frame rate can be re-
duced from the default 30 frame/s at VGA resolu-
tion to less than 3 frame/s at VGA resolution.
3.5.2 PLL and Clock Input
A PLL IP block is embedded. This block generates
all necessary internal clocks from an input range
defined in Table 5. The input clock pad accepts up
to 26 MHz signals.
Table 5. System Input Clock Frequency Range
System clock frequency^a
Min. (MHz)
Max. (MHz)
6.5
26
a.The standard supported input frequencies (in MHz) are as
follows: 6.5, 8.4, 9, 9.6, 9.72, 12,13, 16.8, 18, 19.2,
19.44, 26.
3.5.3 Clock Input Type
VS6552 can receive the following clock types:
■ Single ended CMOS
■ Single ended Sine wave
■ Clock can be AC or DC coupled
The clock is fail-safe.
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