STLVD111_07 Datasheet, PDF (8/19 Pages) STMicroelectronics – Programmable low voltage 1:10 differential LVDS clock driver

Specification of control register
4
Specification of control register
STLVD111
The STLVD111 is provided with a 11 bit shift register with a Serial In and a Control Register.
The purpose is to enable or power of each output clock channel and to select the clock
input. The STLVD111 provides two working modality:
4.1
Programmed mode (EN=1)
The shift register have a serial input to load the working configuration. Once the
configuration is loaded with 11 clock pulse, another clock pulse load the configuration into
the control register. The first bit on the serial input line enables the outputs Q9 and Q9, the
second bit enables the outputs Q8 and Q8 and so on. The last bit is the clock selection bit.
To restart the configuration of the shift register a reset of the state machine must be done
with a clock pulse on CK and the EN set to Low. The control register shift register can be
configured on time after each reset.
4.2
Standard mode (EN=0)
In Standard Mode the STLVD111 isn’t programmable, all the clock outputs are enabled. The
LVDS clock input is selected from Clock 0 or Clock 1 with the SI pin as shown in the Truth
Table below.
Table 10.
EN
L
L
H
H
L
Truth table of state machine inputs
SI
CK
Output
L
X
All output enabled, Clock 0 selected, control register disabled
H
X
All output enabled, Clock 1 selected, control register disabled
L
First stage stores "L", other stages store the data of previous stage
H
First stage stores "H", other stages store the data of previous stage
X
Reset of the state machine, shift register and control register
Table 11. Serial input sequence
BIT#10 BIT#9 BIT#8 BIT#7
CLK_SEL Q0
Q1
Q2
BIT#6
Q3
BIT#5
Q4
BIT#4
Q5
BIT#3
Q6
BIT#2
Q7
BIT#1
Q8
BIT#0
Q9
Table 12.
Truth table of the control register
BIT#10
BIT#(0-9)
L
H
H
H
X
L
Qn(0-9)
Clock 0
Clock 1
Qn Output Disabled
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