SPEAR300 Datasheet, PDF (8/83 Pages) STMicroelectronics – Embedded MPU with ARM926 core, flexible memory support, powerful connectivity features and human machine interface

Description
1
Description
SPEAr300
The SPEAr300 is a member of the SPEAr family of embedded MPUs for networked devices.
It is based on the powerful ARM926EJ-S processor (up to 333 MHz), widely used in
applications where high computation performance is required.
In addition, SPEAr300 has an MMU that allows virtual memory management -- making the
system compliant with advanced operating systems like Linux. It also offers 16 KB of data
cache, 16 KB of instruction cache, JTAG and ETM (embedded trace macro-cell) for debug
operations.
A full set of peripherals allows the system to be used in many applications, some typical
applications being HMI, Security and VoIP phones.
Figure 1. Functional block diagram
NAND/NOR
Flash controller
SDIO/MMC
Mobile DDR/DDR2
memory controller
Serial Flash Interface
32 KBytes BootRom
57 KBytes SRAM
ADC 10-bit 8 ch
JPEG Codec
accelerator
C3 Crypto
accelerator
Multichannel DMA
controller
I2S full duplex
TDM master/slave
USB Device 2.0 +Phy
USB Host 2.0 +Phy
USB Host 2.0 +Phy
Interrupt
Controller
RTC
Watchdog
System
Controller
Timers
PLLs
MMU
ICache
DCache
ARM926EJ-S
@ 333 MHz
JTAG/Trace
Ethernet 10/100
(MII interface)
1-bit DAC
Camera Interface
LCD Controller
1024*768
9*9 keyboard
controller
I²C master/slave
UART and IrDA
SSP
Up to 62 GPIOs
= Functions with shared I/Os depending on the device configuration. Refer to
the pin description
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Doc ID 16324 Rev 2