SPEAR300 Datasheet, PDF (11/83 Pages) STMicroelectronics – Embedded MPU with ARM926 core, flexible memory support, powerful connectivity features and human machine interface

SPEAr300
2
Architecture overview
Architecture overview
The SPEAr300 internal architecture is based on several shared subsystem logic blocks
interconnected through a multilayer interconnection matrix.
The switch matrix structure allows different subsystem dataflow to be executed in parallel
improving the core platform efficiency.
High performance master agents are directly interconnected with the memory controller
reducing the memory access latency. The overall memory bandwidth assigned to each
master port can be programmed and optimized through an internal efficient weighted round-
robin arbitration mechanism.
Figure 2. SPEAr300 overview
NAND Flash
NOR Flash
SRAM
Flash
EEPROM
DDR2
Mobile DDR
MMC
SD-Card
SDIO
Debug, trace
Keypad
controller
TouchScreen
Phy
Internet
access
FSMC
GPIO
SMI
DDR
memory
controller
SDIO/MMC
JTAG
ADC
LCD controller
SPEAr300
ARM 926EJ
up to 333 MHz
8-channel DMA
3 Timers / WD
JPEG Codec
accelerator
C3 Crypto
accelerator
57 KB embed. SRAM
32 KB embed. ROM
MMU
Interrupt/syst controller
Standard OS
support
ETM9
RTC
Clock, reset
Camera
interface
TDM
USB2.0 PHY
USB2.0 PHY
USB2.0 PHY
IdDA
I2C
I2S
24 MHz 32 kHz
External
CODEC/SLICs
Audio
CODECs
2.1
Note: Some interfaces share I/Os. Not all interfaces shown in the figure can be used
concurrently
ARM926EJ-S CPU
The core of the SPEAr300 is an ARM926EJ-S reduced instruction set computer (RISC)
processor.
It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off
between high performance and high code density and includes features for efficient
execution of Java byte codes.
The ARM CPU and is clocked at a frequency up to 333 MHz. It has a 16-Kbyte instruction
cache, a 16-Kbyte data cache, and features a memory management unit (MMU) which
makes it fully compliant with Linux and WindowsCE operating systems.
It also includes an embedded trace module (ETM Medium+) for real-time CPU activity
tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed
trace mode, with normal or half-rate clock.
Doc ID 16324 Rev 2
11/83