M27C2001_99 Datasheet, PDF (8/16 Pages) STMicroelectronics – 2 Mbit (256Kb x 8) UV EPROM and OTP EPROM

M27C2001
Figure 6. Programming and Verify Modes AC Waveforms
A0-A17
Q0-Q7
VPP
VCC
E
P
G
tAVPL
DATA IN
tQVPL
tVPHPL
tVCHPL
tELPL
tPLPH
VALID
tPHQX
DATA OUT
tGLQV
tQXGL
tGHQZ
tGHAX
PROGRAM
VERIFY
AI00720
Figure 7. Programming Flowchart
VCC = 6.25V, VPP = 12.75V
n=0
NO
++n
= 25
YES
P = 100µs Pulse
NO
VERIFY
YES
++ Addr
FAIL
Last NO
Addr
YES
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
AI00715C
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Pro-
gramming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides the
necessary margin to each programmed cell.
Program Inhibit
Programming of multiple M27C2001s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C2001 may be common. A TTL low level
pulse applied to a M27C2001’s P input, with E low
and V_PP at 12.75V, will program that M27C2001.
A high level E input inhibits the other M27C2001s
from being programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
and G at V_IL, P at V_IH, V_PP at 12.75V and V_CC at
6.25V.
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