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STM32F051R6T6 Datasheet, PDF (72/104 Pages) STMicroelectronics – Low- and medium-density advanced ARM-based 32-bit MCU
STM32F051x
Electrical characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 18).
● The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 18).
Output voltage levels
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 20. All I/Os are CMOS and TTL compliant (FT, TTa or TC unless otherwise specified).
Table 51. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
VOL(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
CMOS port(2)
-
0.4
IIO = +8 mA
V
VOH(3)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
2.7 V < VDD < 3.6 V VDD–0.4
-
VOL (1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
TTL port(2)
-
IIO =+ 8mA
VOH (3)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
2.7 V < VDD < 3.6 V
2.4
0.4
V
-
VOL(1)(4)
Output low level voltage for an I/O pin
when 5 pins are sunk at same time
IIO = +20 mA
-
1.3
V
VOH(3)(4)
Output high level voltage for an I/O pin
when 5 pins are sourced at same time
2.7 V < VDD < 3.6 V VDD–1.3
-
VOL(1)(4)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
IIO = +6 mA
-
0.4
V
VOH(3)(4)
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
2 V < VDD < 2.7 V VDD–0.4
-
VOLFM+
Output low level voltage for an FTf I/O
pin in FM+ mode
IIO = +20 mA
2.7 V < VDD < 3.6 V
-
0.4 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 18
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 18 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Data based on characterization results, not tested in production.
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