STA323WQS Datasheet, PDF (71/78 Pages) STMicroelectronics – 2.1-channel high-efficiency digital audio system with QSound QHD®

STA323WQS
User-programmable settings
8.9
Fault detect recovery (address 0x2B - 0x2C)
FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is active, the
TRISTATE output immediately goes low and is held low for the time period specified by this
constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default
value of 0x000C specifies approximately 0.1 ms.
D7
FRDC15
0
FDRC7
0
D6
FDRC14
0
FDRC6
0
D5
FDRC13
0
FDRC5
0
D4
FDRC12
0
FDRC4
0
D3
FDRC11
0
FDRC3
1
D2
FDRC10
0
FDRC2
1
D1
FDRC9
0
FDRC1
0
D0
FDRC8
0
FDRC0
0
8.10 Status indicator register (address 0x2D)
8.10.1
8.10.2
D7
D6
D5
D4
D3
D2
D1
D0
PLULL
FAULT
TWARN
0
1
1
STATUS register bits serve the purpose of communicating the detected error or warning
condition to the user. This is a read-only register and writing to this register would not be of
any consequence.
Thermal warning indicator
Table 70. Thermal warning indicator
Bit
R/W
RST
Name
Description
0: thermal warning detected
0
RO
1
RWRAN
1: normal operation (no thermal warning)
If the power stage thermal operating conditions are exceeded, the thermal warning indicator
transmits a signal to the digital logic block to initiate a corrective procedure. This register bit
is set to 0 to indicate a thermal warning and it reverts back to its default state as soon as the
cause of the thermal warning has been corrected.
Fault detect indicator
Table 71. Fault detect indicator
Bit
R/W
RST
Name
Description
0: fault issued from the power stage
1
RO
1
FAULT
1: normal operation (no fault)
As soon as the power stage issues a Fault error signal, thereby initiating the Fault recovery
procedure described in Section 8.9, this register bit is set to 0 to indicate the error to the
user. As soon as the fault condition (over-current or thermal) is corrected, this bit is reset
back to its default state.
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