STA323WQS Datasheet, PDF (49/78 Pages) STMicroelectronics – 2.1-channel high-efficiency digital audio system with QSound QHD®

STA323WQS
Register descriptions
Table 44. Output configuration selections
OCFG[1:0]
Output power configuration
2 channel (full-bridge) power, 1 channel DDX:
00
1A/1B ◊ 1A/1B
2A/2B ◊ 2A/2B
2(half-bridge).1(full-bridge) on-board power:
1A ◊ 1A
Binary
01
2A ◊ 1B
Binary
3A/3B ◊ 2A/2B Binary
10
Reserved
1 channel mono-parallel:
11
3A ◊ 1A/1B
3B ◊ 2A/2B
Table 45. Invalid input detect mute enable
Bit R/W RST Name
Description
2
RW 1
0: disabled
IDE
1: enabled
Setting the IDE bit enables this function, which looks at the input I²S data and clocking and
automatically mutes all outputs if the signals are invalid.
Table 46. Binary clock loss detection enable
Bit R/W RST Name
Description
5
RW 1
BCLE
0: disabled
1: enabled
Detects loss of input MCLK in binary mode and outputs 50% duty cycle to prevent audible
noise when input clocking is lost.
Table 47. Auto-EAPD on clock loss enable
Bit R/W RST Name
Description
7
RW 0
ECLE
0: disabled
1: enabled
When ECLE is active, it issues a power device power down signal (EAPD) on clock loss
detection.
Table 48. External amplifier power down
Bit R/W RST Name
Description
7
RW 0
EAPD
0: external power stage power down active
1: normal operation
EAPD is used to actively power down a connected DDX^® power device. This register has to
be written to 1 at start-up to enable the DDX^® power device for normal operation.
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