PM0253 Datasheet, PDF (71/252 Pages) –

PM0253
The Cortex-M7 instruction set
3.3.8
Example 3-2: compare and update value shows the use of conditional instructions to update
the value of R4 if the signed values R0 is greater than R1 and R2 is greater than R3.
Example 3-2: compare and update value
CMP
R0, R1
ITT
GT
CMPGT R2, R3
MOVGT R4, R5
; Compare R0 and R1, setting flags.
; Skip next two instructions unless GT condition
; holds.
; If 'greater than', compare R2 and R3, setting
; flags.
; If still 'greater than', do R4 = R5.
Instruction width selection
There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding
depending on the operands and destination register specified. For some of these
instructions, a specific instruction size can be forced by using an instruction width suffix.
The .W suffix forces a 32-bit instruction encoding. The .N suffix forces a 16-bit instruction
encoding.
If an instruction width suffix is specified and the assembler cannot generate an instruction
encoding of the requested width, it generates an error.
In some cases it might be necessary to specify the .W suffix, for example if the operand is
the label of an instruction or literal data, as in the case of branch instructions. This is
because the assembler might not automatically generate the right size encoding.
To use an instruction width suffix, place it immediately after the instruction mnemonic and
condition code, if any. Example 3-3: instruction width selection shows instructions with the
instruction width suffix.
Example 3-3: instruction width selection
BCS.W label
; Creates a 32-bit instruction even for a short
; branch.
ADDS.W R0, R0, R1 ; Creates a 32-bit instruction even though the same
; operation can be done by a 16-bit instruction.
DocID028474 Rev 3
71/252
182