PM0253 Datasheet, PDF (122/252 Pages) –

The Cortex-M7 instruction set
PM0253
3.6.8
Examples
SMMLA
SMMLAR
SMMLSR
SMMLS
R0, R4, R5, R6
R6, R2, R1, R4
R3, R6, R2, R7
R4, R5, R3, R8
; Multiplies R4 and R5, extracts top 32 bits,
; adds R6, truncates and writes to R0.
; Multiplies R2 and R1, extracts top 32 bits,
; adds R4, rounds and writes to R6.
; Multiplies R6 and R2, extracts top 32 bits,
; subtracts R7, rounds and writes to R3.
; Multiplies R5 and R3, extracts top 32 bits,
; subtracts R8, truncates and writes to R4.
SMMUL
Signed Most Significant Word Multiply.
Syntax
op{R}{cond} Rd, Rn, Rm
Where:
op
Is one of:
SMMUL Signed Most Significant Word Multiply
R
Is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond
Is an optional condition code. See Conditional execution on page 68.
Rd
Is the destination register.
Rn, Rm Are registers holding the first and second operands.
Operation
The SMMUL instruction interprets the values from Rn and Rm as two’s complement 32-bit
signed integers. The SMMUL instruction:
• Multiplies the values from Rn and Rm.
• Optionally rounds the result, otherwise truncates the result.
• Writes the most significant signed 32 bits of the result in Rd.
Restrictions
In this instruction:
• Do not use SP and do not use PC.
Condition flags
This instruction does not affect the condition code flags.
Examples
SMULL
SMULLR
R0, R4, R5
R6, R2
; Multiplies R4 and R5, truncates top 32 bits
; and writes to R0.
; Multiplies R6 and R2, rounds the top 32
; bits and writes to R6.
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