ST72321BXXX-AUTO Datasheet, PDF (70/247 Pages) STMicroelectronics – 8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM, ADC, 5 timers, SPI, SCI, I2C interface

Power saving modes
ST72321Bxxx-Auto
Table 26. MCC/RTC low power mode selection
MCCSR OIE bit
Power saving mode entered when HALT instruction is executed
0
Halt
1
Active Halt
8.4.1
Note:
Caution:
Active Halt mode
Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock
Controller Status register (MCCSR) is set (see Section 12.3: ART registers for more details
on the MCCSR register).
The MCU can exit Active Halt mode on reception of an external interrupt, MCC/RTC
interrupt or a RESET. When exiting Active Halt mode by means of an interrupt, no 256 or
4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Figure 26).
When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in Active Halt mode is provided by the oscillator
interrupt.
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering Active Halt mode while the Watchdog is active does not generate a RESET.
This means that the device cannot spend more than a defined delay in this power saving
mode.
When exiting Active Halt mode following an MCC/RTC interrupt, OIE bit of MCCSR register
must not be cleared before t_DELAY after the interrupt occurs (t_DELAY = 256 or 4096 t_CPU
delay depending on option byte). Otherwise, the ST7 enters Halt mode for the remaining
t_DELAY period.
Figure 25. Active Halt timing overview
ACTIVE _{256 OR 4096 CPU}
RUN HALT
CYCLE DELAY⁽¹⁾
RUN
HALT
INSTRUCTION
[MCCSR.OIE = 1]
RESET
OR
INTERRUPT
FETCH
VECTOR
1. This delay occurs only if the MCU exits Active Halt mode by means of a RESET.
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