ST72321BXXX-AUTO Datasheet, PDF (48/247 Pages) STMicroelectronics – 8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM, ADC, 5 timers, SPI, SCI, I2C interface

Supply, reset and clock management
ST72321Bxxx-Auto
6.5.3
6.5.4
6.5.5
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in Chapter 19:
Electrical characteristics.
If the external RESET pulse is shorter than t_w(RSTL)out (see short ext. Reset in Figure 13),
the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see
long ext. Reset in Figure 13). Starting from the external RESET pulse recognition, the
device RESET pin acts as an output that is pulled low during at least t_w(RSTL)out.
External power-on RESET
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V_DD is over
the minimum level specified for the selected f_OSC frequency (see Section 19.3: Operating
conditions on page 193).
A proper reset signal for a slow rising V_DD supply can generally be provided by an external
RC network connected to the RESET pin.
Internal low voltage detector (LVD) RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
● Power-on RESET
● Voltage drop RESET
The device RESET pin acts as an output that is pulled low when V_DD < V_IT+ (rising edge) or
V_DD < V_IT- (falling edge) as shown in Figure 13.
The LVD filters spikes on V_DD larger than t_g(VDD) to avoid parasitic resets.
Internal watchdog RESET
The RESET sequence generated by an internal Watchdog counter overflow is shown in
Figure 13.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t_w(RSTL)out.
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