TDA7479_08 Datasheet, PDF (7/12 Pages) STMicroelectronics – Single chip RDS demodulator + filter

TDA7479
3
Output timing
Output timing
The RDS (1187.5Hz) output clock on RDCL line is synchronized to the incoming data. According
to the internal PLL lock condition data change can result on the falling or on the rising clock edge
(see Figure 3). Whichever clock edge is used by the decoder (rising or falling edge) the data will
remain valid for 416.7 µs after the clock transition.
Figure 3. RDS timing diagram
RDCL
RDDA
4.3µs 837.7µs
td
421µs 421µs 4.3µs
CLOCK
LINE
DATA
LINE
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