M50LPW116 Datasheet, PDF (7/36 Pages) STMicroelectronics – 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory

Table 5. Block Addresses
Size
(Kbytes)
Address Range
Block
Number
Block
Type
16 1FC000h-1FFFFFh 49 Boot (Top)
8
1FA000h-1FBFFFh 48 Parameter
8
1F8000h-1F9FFFh
47 Parameter
32
1F0000h-1F7FFFh
46
Main
64 1E0000h-1EFFFFh 45
Main
64 1D0000h-1DFFFFh 44
Main
64 1C0000h-1CFFFFh 43
Main
64 1B0000h-1BFFFFh 42
Main
64 1A0000h-1AFFFFh 41
Main
64
190000h-19FFFFh
40
Main
64
180000h-18FFFFh
39
Main
64
170000h-17FFFFh
38
Main
64
160000h-16FFFFh
37
Main
64
150000h-15FFFFh
36
Main
64
140000h-14FFFFh
35
Main
64
130000h-13FFFFh
34
Main
64
120000h-12FFFFh
33
Main
64
110000h-11FFFFh
32
Main
64
100000h-10FFFFh
31
Main
64 0F0000h-0FFFFFh 30
Main
64 0E0000h-0EFFFFh 29
Main
64 0D0000h-0DFFFFh 28
Main
64 0C0000h-0CFFFFh 27
Main
64 0B0000h-0BFFFFh 26
Main
M50LPW116
64 0A0000h-0AFFFFh 25
Main
64
090000h-09FFFFh
24
Main
64
080000h-08FFFFh
23
Main
64
070000h-07FFFFh
22
Main
64
060000h-06FFFFh
21
Main
64
050000h-05FFFFh
20
Main
64
040000h-04FFFFh
19
Main
64
030000h-03FFFFh
18
Main
64
020000h-02FFFFh
17
Main
64
010000h-01FFFFh
16
Main
4
00F000h-00FFFFh 15 Parameter
4
00E000h-00EFFFh 14 Parameter
4
00D000h-00DFFFh 13 Parameter
4
00C000h-00CFFFh 12 Parameter
4
00B000h-00BFFFh 11 Parameter
4
00A000h-00AFFFh 10 Parameter
4
009000h-009FFFh
9
Parameter
4
008000h-008FFFh
8
Parameter
4
007000h-007FFFh
7
Parameter
4
006000h-006FFFh
6
Parameter
4
005000h-005FFFh
5
Parameter
4
004000h-004FFFh
4
Parameter
4
003000h-003FFFh
3
Parameter
4
002000h-002FFFh
2
Parameter
4
001000h-001FFFh
1
Parameter
4
000000h-000FFFh
0
Parameter
Note: For A21 and A23, refer to Table 2. A22 is set to 1.
LAD3. On the following Clock cycles the Host will
send the Cycle Type + Dir, Address, other control
bits, Data0-Data3 and Data4-Data7 on LAD0-
LAD3. The memory outputs Sync data until the
wait-states have elapsed.
See Table 7, and to Figure 5, for a description of
the Field definitions for each clock cycle of the
transfer. See Table 22, and Figure 9, for details on
the timings of the signals.
Bus Abort. The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when LFRAME is driven Low,
V_IL, during the bus operation; the memory will tri-
state the Input/Output Communication pins,
LAD0-LAD3.
Note that, during a Bus Write operation, the
Command Interface starts executing the
command as soon as the data is fully received; a
Bus Abort during the final TAR cycles is not
guaranteed to abort the command; the bus,
however, will be released immediately.
Standby. When LFRAME is High, V_IH, the
memory is put into Standby mode where LAD0-
LAD3 are put into a high-impedance state and the
Supply Current is reduced to the Standby level,
I_CC1.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP, or CPU
Reset, INIT, is Low, V_IL. RP or INIT must be held
7/36