M50LPW116 Datasheet, PDF (1/36 Pages) STMicroelectronics – 16 Mbit 2Mb x8, Boot Block 3V Supply Low Pin Count Flash Memory

M50LPW116
16 Mbit (2Mb x8, Boot Block)
3V Supply Low Pin Count Flash Memory
PRELIMINARY DATA
s SUPPLY VOLTAGE
– V_CC = 3V to 3.6V for Program, Erase and
Read Operations
– V_PP = 12V for Fast Program and Fast Erase
s TWO INTERFACES
– Low Pin Count (LPC) Standard Interface for
embedded operation with PC Chipsets.
– Address/Address Multiplexed (A/A Mux) In-
terface for programming equipment compati-
bility.
s LOW PIN COUNT (LPC) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface supporting
Read and Write Operations
– Hardware Write Protect Pins for Block Pro-
tection
– Register Based Read and Write Protection
– 5 Additional General Purpose Inputs for plat-
form design flexibility
– Synchronized with 33 MHz PCI clock
s BYTE PROGRAMMING TIME
– Single Byte Mode: 10µs (typical)
– Quadruple Byte Mode: 2.5µs (typical)
s 50 MEMORY BLOCKS
– 1 Boot Block
– 18 Parameter and 31 Main Blocks
s PROGRAM/ERASE CONTROLLER
– Embedded Byte Program and Block/Chip
Erase algorithms
– Status Register Bits
s PROGRAM and ERASE SUSPEND
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 30h
TSOP40 (N)
10 x 20mm
Figure 1. Logic Diagram (LPC Interface)
VCC VPP
4
ID0-ID3
5
GPI0-
GPI4
4
LAD0-
LAD3
WP
LFRAME
M50LPW116
TBL
CLK
IC
RP
INIT
VSS
AI05466
February 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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