HCC4047B Datasheet, PDF(7/15 Page) STMicroelectronics – LOW-POWELOW-POWER MONOSTABLE/ASTABLE MULTIVIBRATOR

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HCC4047B Datasheet, PDF (7/15 Pages) STMicroelectronics – LOW-POWELOW-POWER MONOSTABLE/ASTABLE MULTIVIBRATOR

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Typical Output High (source) Current Charac-

teristics.

HCC/HCF4047B

Minimum Output High (source) Current Charac-

teristics.

APPLICATION INFORMATION

1 - CIRCUIT DESCRIPTION

Astable operation is enabled by a high level on the

ASTABLE input. The period of the square wave at

the Q and Q Outputs in this mode of operation is a

function of the external components employed.

âTrueâ input pulses on the ASTABLE input or âCom-

plementâ pulses on the ASTABLE input allow the cir-

cuit to be used as a gatable multivibrator. The

OSCILLATOR output period will be half of the Q ter-

minal output in the astable mode. However, a 50%

duty cycle is not guaranteed at this output. In the

monostable mode, positive-edge triggering is ac-

complished by application of a leading-edge pulse

to the +TRIGGER input and a low level to the âTRI-

GGER input. For negative-edge triggering, a trail-

ing-edge pulse is applied to the âTRIGGER and a

high level is applied to the +TRIGGER. Input pulses

may be of any duration relative to the output pulse.

The multivibrator can be retriggered (on the leading

edge only) by applying a common pulse to both the

RETRIGGER and +TRIGGER inputs. In this mode

the output pulse remains high as long as the input

pulse period is shorter than the period determined

by the RC components. An external countdown op-

tion can be implemented by coupling âQâ to an ex-

ternal âNâ counter and resetting the counter with the

trigger pulse. The counter output pulse is fed back

to the ASTABLE input and has a duration equal to

N times the period of the multivibrator. A high level

on the EXTERNAL RESET input assures no output

pulse during an âONâ power condition. This input

can also be activated to terminate the output pulse

at any time. In the monostable mode, a high-level or

power-on reset pulse, must be applied to the EX-

TERNAL RESET whenever VDD is applied.

2 - ASTABLE MODE

The following analysis presents worst-case vari-

ations from unit-to-unit as a function of transfer-volt-

age (VTR) shift (33% â 67% VDD) for free-running

(astable) operation.

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