ESDAVLC6V1-1BM2 Datasheet, PDF (7/13 Pages) STMicroelectronics – Single line low capacitance Transil for ESD protection

ESDAVLC6V1-1BM2, ESDAVLC6V1-1BT2
3
Package information
Package information
● Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK^®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Table 3. SOD882 dimensions
INDEX AREA
(D/2 x E/2)
TOP VIEW
D
E
SIDE VIEW
A
A1
BOTTOM VIEW
b1
b2
INDEX AREA
(D/2 x E/2)
L1
L2
OPTIONAL
PIN # 1 ID
e
Dimensions
Ref. Millimeters
Inches
Min. Typ. Max. Min. Typ. Max.
A 0.40 0.47 0.50 0.016 0.019 0.020
A1 0.00
0.05 0.000
0.002
b1 0.20 0.25 0.30 0.008 0.010 0.012
b2 0.20 0.25 0.30 0.008 0.010 0.012
D
1.00
0.039
E
0.60
0.024
e
0.65
0.026
L1 0.45 0.50 0.55 0.018 0.020 0.022
L2 0.45 0.50 0.55 0.018 0.020 0.022
Figure 21. Footprint
Figure 22. Marking
0.55
0.55
0.50
0.40
Pin1
C
Pin 2
Note:
Product marking may be rotated by 90° for assembly plant differentiation. In no case should
this product marking be used to orient the component for its placement on a PCB. Only pin
1 mark is to be used for this purpose.
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