CM17699 Datasheet, PDF (7/11 Pages) STMicroelectronics – COLOR PDP DRIVER MODULE

CM17699
6 - STV7699 SPECIFICATIONS (continued)
6.4 - Block Diagram
CLK
A1
A2
A3
A4
STB
BLK
POL
16-BIT SHIFT REGISTER
P1
P61
16-BIT SHIFT REGISTER
P2
P62
16-BIT SHIFT REGISTER
P3
P63
16-BIT SHIFT REGISTER
P4
P64
P1
P4
Q1 Q2
LATCH
P63 P64
Q63Q64
HIZ
STV7699
2
OUT1
79
OUT64
F/R
B1
B2
B3
B4
V_CC
V_SSLOG
Pins 90 to 93
V_SSSUB
Pins 41-81
V_SSP
Pins 6-15-24-35
40-46-57-66-75
V_PP
Pins 1-29-30
51-52-80
6.5 - Circuit Description
STV7699 contains all the logic and the power
circuits necessary to drive the colums of a Plasma
Display Panel (P.D.P.). Data are shifted at each low
to high transition of the (CLK) shift clock. Data are
input in a 4-bit wide data bus to A1 - A4 input (case
of forward shift mode ; F/R = low). After 16 shifts,
the first nibble is available at the serial outputs
B1 - B4. These outputs can be used to cascade
several drivers to perform any horizontal resolution.
CLK, Ai and Bi inputs are Smith trigger inputs to
improve the noise margin.
The Forward/Reverse (F/R) input is used to select
the direction of the shift register.
The maximum frequency of the shift clock is
20MHz.
All the output data are held and memorized into the
latch stage when the Latch input (STB) is high.
When it is at low level, data are transferred from
the shift register to the latch and to the output power
stage.
Output state can be forced to high impedance by
pulling low HIZ input.
When BLK is Low, all the outputs are forced to low
level or high level according to POL signal value.
Output state copy data that was input, with the
same polarity, when BLK, HIZ and POL are High.
VSSLOG, VSSSUB and VSSP are not internally con-
nected.
VSSLOG and VSSSUB must be connected as close as
possible to the logical reference ground of the
application.
Table 1 : Power Output Truth Table
Data
STB
POL
BLK
HIZ
Driver
Output
Comments
x x x x L HIZ High impedance
x x L x H L Forced to low
x x H L H H Forced to high
x H H H H Qn (1) Latched data
L L H H H L Copy data
H L H H H H Copy data
Note 1 : Qn is the value memorised in the latch stage ; it is the value
of the parallel shift register output stage after n Clock
pulses.
A data loaded in the shift register is read on the
output power stage without inversion of its polarity.
Table 2 : Control Table
F/R
Ai
Bi
Comments
L
Input Output Forward shift
H Output Input Reverse shift
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